D-Wave Quantum Inc. Common Stock 2026 Q2 Earnings Call

Please go ahead. Thank you, and good morning.

With me today are Dr. Alan Baratz, our Chief Executive Officer, and Jon Markowicz, our Chief Financial Officer. Before we begin, I would like to remind everyone that this call will contain forward-looking statements, which are subject to risks and uncertainties and should be considered in conjunction with cautionary statements contained in our earnings release and the company's most recent periodic SEC reports. Both an on-demand webcast and a transcript of the conference call will be available on the investor relations section of the website within 48 hours after the call. During today's call, management will provide certain information that will constitute non-GAAP financial measures under SEC rules, such as adjusted EBITDA loss and non-GAAP adjusted operating expenses and operating metrics such as bookings.

Reconciliations to GAAP financial measures and certain additional information are also included in today's earnings release, which is available in the investor relations section of our company website at ir.dwavequantum.com. This morning, we will be limited to taking one question from each analyst in the first round of questions, and then, time permitting, proceed to a second round of questions where again, we'll limit each analyst to one question. I'll now hand over the call to Alan.

Good morning, everyone, and thank you for joining us. The quantum computing market is reaching an important inflection point. Scientific progress is accelerating, customer interest is expanding, and a growing number of companies are entering the public markets. That increased visibility is good for the industry, but it also means investors need to separate measurable progress from rhetoric. In a market increasingly crowded with claims, investors should ask three simple questions. First, does the company have differentiated technology with a credible path to scale? Second, can the company translate that technology into reliable, enterprise-ready systems? Third, can it execute and produce measurable customer value? At our recent Investor Day, we demonstrated why we believe that D-Wave stands apart on each of these three criteria.

We have a differentiated technical foundation, deep expertise building and operating commercial quantum systems, a growing portfolio of production applications, and clear roadmaps across our dual platform strategy. This quarter added further evidence. IDC recently named D-Wave as one of only two companies in the leaders category in the IDC MarketScape: Worldwide Quantum Computing 2026 Vendor Assessment. We believe this recognition is significant because IDC evaluated companies not simply on a single performance metric or future roadmap, but on both their current capabilities and their ability to execute. IDC highlighted D-Wave's production deployment footprint, our mature framework for enterprise access and hybrid adoption, and our work extending annealing quantum computing beyond optimization and into scientific simulation. It also observed that competition in quantum computing is shifting away from raw qubit counts and towards broader platform maturity.

That includes software, hybrid integration, deployment flexibility, and integration with existing HPC, AI, and enterprise computing environments. In other words, the industry is increasingly being judged on whether companies can deliver complete, usable quantum platforms, not simply announce ambitious roadmaps, and that plays directly to D-Wave's strengths. Quantum computing leadership requires far more than a promising processor. It requires hardware, cryogenics, control systems, software, cloud infrastructure, developer tools, professional services, and the operating discipline to make the entire stack perform reliably. We have spent more than 15 years doing that hard work. Let me now turn to the technical developments announced this quarter and the roadmaps they support. Our objective for D-Wave's Gate Model program is clear: to deliver a fast, scalable, and commercially useful, fault-tolerant quantum computer. The threshold for commercial relevance is high.

We believe that initial commercial applications will require approximately 100 logical qubits and the ability to perform more than 1 million operations reliably. A system that cannot reach both sufficient scale and sufficient reliability may be scientifically interesting, but it is not yet capable of addressing commercially meaningful problems. That is the standard investors should apply when evaluating gate model roadmaps. Reaching that threshold requires much more than increasing physical qubit counts. A system must have computational capacity, fast gate operations, and an error correction architecture that can scale efficiently. Error correction is essential because physical qubits are inherently susceptible to errors. Without effective error correction, a gate model system cannot reliably execute the long and complex computations required to solve meaningful problems.

That's why we believe investors and customers should evaluate gate model architectures using three fundamental measures: how quickly can the system perform gate operations and error correction cycles? How efficiently do errors decline as error correction capability is added? And when will the system support enough reliable operations on enough logical qubits to address commercially relevant applications? At our investor day, we detailed how D-Wave's superconducting dual-rail architecture is designed to address these requirements. Superconducting technology provides an important speed advantage, with gate operations and error correction cycles performed on microsecond timescales. At smaller system sizes, differences in speed may appear less consequential. At commercial scale, when a system must execute enormous numbers of operations and error correction cycles, speed becomes fundamental to whether it can solve a problem within a commercially relevant timeframe.

The other critical measure is Lambda, which describes how rapidly logical errors decline as the size of the error-correcting code increases. A higher Lambda means each additional increment of error correction produces a greater reduction in errors, lowering the number of physical qubits required to create a reliable logical qubit. Leading superconducting approaches have demonstrated a Lambda of approximately two, meaning errors decline by roughly a factor of two with each increment in the error-correcting code. Our gate model roadmap targets a Lambda of 10. This target is grounded in the inherent error detection characteristics of our dual-rail architecture, the performance that we have already demonstrated on our system, and the recent peer-reviewed results validating that those advantages are preserved during high-fidelity entangling operations. Taken together, this evidence gives us confidence in our ability to achieve significantly more efficient error correction as the architecture scales.

A Lambda of 10 would reduce errors by a factor of 10 with each increment in error-correcting code. At scale, that level of efficiency could enable approximately 100-200 physical qubits to produce one reliable logical qubit, rather than the many thousands that may be required by less efficient superconducting approaches. That is not a marginal improvement. It is transformational. It fundamentally changes the size, complexity, and hardware overhead required to reach fault tolerance. We believe this combination of superconducting speed and highly efficient error correction is the core differentiation behind D-Wave's gate model architecture, and an important reason we believe our approach offers an efficient and achievable path to commercial fault tolerance. The peer-reviewed research that we announced yesterday provides important validation of that foundation. Published in Nature, the research demonstrates a fast, high-fidelity, two-qubit entangling gate designed to support efficient quantum error correction.

The research demonstrated approximately 99.9% fidelity during two-qubit operations, with fast gate times of about 500 nanoseconds, all enabled by native hardware-level error detection and no additional error correction. Why is this significant? The results address one of the industry's most consequential challenges by reducing the immense quantum and classical hardware overhead typically required to detect and correct quantum errors as systems scale. It also addresses a longstanding challenge for superconducting quantum computers, which are known for their speed but have historically struggled to achieve the high fidelity required for scalable fault-tolerant systems. The Nature paper validates that our dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving native hardware-level error detection.

Our simulations indicated that our dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction, significantly reducing the physical overhead required for fault-tolerant quantum computing. We believe these results provide strong technical evidence that the architectural principles underlying our roadmap can support faster, more hardware-efficient fault-tolerant quantum computing than any other approach to gate model quantum computing. Importantly, this is not isolated laboratory work. The entangling gate demonstrated in the research was done on our eight-qubit dual-rail processor, creating a direct line from peer-reviewed validation to roadmap execution. That architectural foundation supports the gate model roadmap that we presented at our investor day, which is designed to progressively demonstrate more effective error detection and correction, lower logical error rates, and increase scale on the path to commercial fault tolerance.

Specifically, later this year, we expect to deliver a 17 physical qubit system designed to support logical error rates approximately 2 times lower than the underlying physical error rates. Next year, we expect to complete a 49 physical qubit system designed to deliver an approximately 20-fold error reduction factor. In 2028, we expect to complete a 181 physical qubit system designed to deliver an approximately 2,000-fold error reduction factor. We expect that system to provide the scalable architectural blueprint for the fault-tolerant systems that follow. By 2030, we expect to complete a system with 10 logical qubits capable of supporting the first fault-tolerant algorithms. By 2032, we expect to scale to 100 logical qubits and more than 1 million reliable operations, creating a system capable of supporting initial commercial applications in areas such as quantum chemistry and quantum AI.