Atomera Incorporated Common Stock 2026 Q3 Earnings Call

Hello everyone, and welcome to Atomera's third quarter 2026 update call. I would like to remind everyone that this call and webinar are being recorded, and a replay will be available on atomera.com's IR website for one year. I am Mike Bishop with the company's investor relations. As in prior quarters, we are using Zoom, and we will follow a similar presentation format, with participants in a listen-only mode. We will open with prepared remarks from Scott Bibaud, Atomera's President and CEO, and Frank Laurencio, Atomera's CFO. Then we will open the call to questions. If you are joining by telephone, you may follow a slide presentation to accompany our remarks on the Events and Presentations section of our Investor Relations page on our website. Before we begin, I would like to remind everyone that during today's call, we will make forward-looking statements.

These forward-looking statements, whether in prepared remarks or during the Q&A session, are subject to inherent risks and uncertainties. These risks and uncertainties are detailed in the Risk Factors section of our filings with the Securities and Exchange Commission, specifically in the company's annual report on Form 10-K filed with the SEC on February 24, 2026. Except as otherwise required by federal securities laws, Atomera disclaims any obligation to update or make revisions to such forward-looking statements contained herein or elsewhere to reflect changes in expectations with regards to those events, conditions, and circumstances. Also, please note that during this call we will be discussing non-GAAP financial measures as defined by SEC Regulation G. Reconciliations of these non-GAAP financial measures to the most directly comparable GAAP measures are included in today's press release, which is posted on our website.

With that, I would like to turn the call over to our President and CEO, Scott Bibaud.

Go ahead, Scott. Thanks, Mike, and good afternoon, everyone.

When I look back on Q3, what stands out is how many long-running efforts came to a head in the last 90 days. We hit a Gate-All-Around target we had publicly committed to in February. We extended MST into a part of the memory market we had never served before, and we turned our GaN-on-silicon breakthrough into a manufacturing relationship with a world-class wafer supplier. Let me take those in order. Gate-All-Around first, then memory, then our power and RF pipeline, and I will close on GaN. Gate-All-Around is quite simply the hardest manufacturing problem the industry is facing today. Building transistors with features thousands of times thinner than a human hair while holding individual dopant atoms exactly where they belong through the downstream thermal budget is precisely the kind of problem MST was created to solve.

Only four companies in the world are developing Gate-All-Around. Back in February, I set a clear objective for the year: to be actively engaged with the leaders driving this transition. Today, I can tell you we have met that objective. We are now engaged with three of the four Gate-All-Around customers, and we remain in active dialogue with the fourth. If our efforts with these players pan out, MST will become a standard ingredient in all future leading-edge logic nodes. While each of these engagements are in a different phase, from the early evaluation stage to running development demonstrations on customer silicon, together they position MST as a solution to one of the biggest challenges confronting teams developing Gate-All-Around nodes and the CFET generation that follows it.

Advanced node customers move deliberately, asking for proof point after proof point before they take any new material into production, so every stage we clear carries weight. Memory is where I see the curve bending upward fastest. The pressure on memory makers to wring more capacity and performance out of every wafer has rarely been greater, and importantly, they have both the urgency and the resources to qualify new approaches. in Q3, we broadened our reach to memory manufacturers spanning both halves of the market, next-generation DRAM and NAND flash. Let me linger on DRAM for a moment because it shows how MST creates value for two different next-gen DRAM requirements. First, AI has driven demand for high-bandwidth memory, which uses leading-edge logic as the base wafer. We are leveraging our Gate-All-Around know-how and using it to help achieve similar gains in these base wafers.

Second, for decades, the industry made DRAM cells smaller with finer lithography, but that lever is nearly exhausted. The next move for some memory makers is a denser cell the industry calls 4F squared, which tips the access transistor up on its end, a vertical channel, and places the storage capacitor above it, shrinking cell area by about a third with no change in lithography. The challenge is building a good vertical transistor, and that is Atomera's opening. We are leveraging our phosphorus blocking know-how from Gate-All-Around to precisely control the dopants, preventing movement into places where they shouldn't be. MST-based vertical transistors can hit the drive current and leakage targets 4F squared requires while stripping out costly process steps. In other words, a cheaper and more manufacturable road to the next DRAM generation.

We laid this out in a peer-reviewed paper at SISPAD in September, the industry's premier conference for process and device simulation, and the response to our paper proved that we were tackling a big problem the industry is grappling with. More importantly, recent visits with the leading memory manufacturers confirmed their interest in just such a solution. NAND is the newer story. As I mentioned last quarter, AI is driving demand for higher density SSDs, which means the number of layers in a 3D NAND device has to keep climbing. But as layer count increases, so does the logic required to drive it, and the CMOS-based die is projected to grow faster than the memory array die sitting above it. Because of that, because the CMOS wafer is bonded to the array, a size mismatch between the two can become an expensive problem.

MST helps solve it by enabling shorter gate lengths so the two die can be sized to match, making for far more cost-effective solutions. These engagements are still early, but they are encouraging, both in terms of the customer problem we are addressing and the real silicon data behind our approach. As you can imagine, the market size is enormous. Across the rest of the pipeline, momentum is steady. Our large ongoing program with a major analog and power manufacturer is tracking to plan. The two engineering teams are in lockstep, executing wafer runs with the objective of including MST in the next node of customer devices. Elsewhere in power and RF SOI, we are moving several new customers forward, putting MST to work on devices like trench FETs and HBTs, whose efficiency and high-frequency behavior matter more by the day as AI data centers reshape how power is delivered.

Internally, our high throughput RF SOI process effort, where locking down the right substrate supply chain is pivotal, keeps advancing and should translate to other applications as well. That brings me to GaN-on-silicon, which was a standout this quarter. Start with the size of the prize. As RF moves to their next generation, designers increasingly reach for GaN because of its raw power and bandwidth, right up to fully integrated front ends that fold in the power amplifier. The RF GaN market sits near $1.2 billion today and is compounding at double digits towards roughly $2 billion within a few years. Moreover, this breakthrough is likely to expand the TAM by opening new applications which integrate with silicon devices at 200 and 300 millimeter wafer sizes.

As a reminder, our breakthrough earlier this year brought MST-enabled GaN-on-silicon within striking distance of advanced RF SOI on the two numbers designers live by, loss and linearity. But on a low-cost silicon wafer rather than a costly specialty substrate that this type of performance has typically demanded. If design activity starts shifting towards GaN-on-silicon, we would be standing at the front of a large and fast-expanding market. In this quarter, we announced something new, a route to manufacturing in the form of a joint development agreement with IQE, announced last week. IQE is among the world's foremost manufacturers of compound semiconductor epitaxy, the precision crystal growth step beneath every GaN wafer. Under the JDA, IQE's GaN epitaxy grown on MST silicon substrates will be optimized to identify the best low-cost, high-performance RF GaN-on-silicon wafers possible.

This work, which has already begun, will allow us to improve performance at the same time we are solving the manufacturing side of the equation, meaning we short circuit the qualification cycle normally required before production. A JDA like this is what moves us from a lab result to a product. IQE gives us a credible high-volume production path and a way to put real sample wafers into the hands of foundry, IDM, and fabless designers. We are starting with RF, but the agreement covers GaN for power as well, broadening the opportunity further. In short, IQE is a catalyst to get MST GaN-on-silicon to market faster, and we believe they can become an important producer of MST-enabled wafers. Atomera offers MST in two forms. One is a blanket deposition that customers can buy and use as a starting wafer, and the other is deposited inside a customer's transistor.

Over the last few years, we've emphasized starting wafer offerings because they're easier for customers to trial and integrate, and therefore represent a faster path to revenue for Atomera. A year ago, we had two applications for those starting wafers, and now we're up to six, including RF SOI, GaN-on-silicon, memory applications, and more. Therefore, today we are introducing the Prima brand for those products. Our more traditional offering, where MST is integrated selectively into the middle of a semiconductor device, will now be known as Selecta. Applications such as Gate-All-Around power devices and HBT use a Selecta process. We're introducing these brand names to highlight the growing importance of starting wafer solutions within Atomera's product portfolio. You'll find much more on Prima Selecta and how MST enhances transistors on our newly refreshed website, which should go live tomorrow.