Qualcomm Inc Deutsche Bank 2026 Technology Conference

Sure. Yeah. I joined Qualcomm in 1998, so it is my 29th year over there. Inside Qualcomm, we have gone through at least two different DNA mutations over the last two and a half decades or so. This is the third one. I ran our research and R&D organization for the longest period of time till about 10 years back or so. That is when Cristiano, who is our CEO now, my boss now, he said, "I want you to come over on this side and help on the business." For the last few years, it has been more than a few years now, eight or nine years, I have been running the product planning.

At this point in time, I run all of our technology roadmap across all the businesses, ranging from this lowest end IoT all the way up to data center. Last year, when we restarted our data center business, I ran the business for one year just to kind of make sure that we are in the right direction, and now we have a full-fledged business unit that is running by itself. That is my role. Awesome.

Yeah. It started off, first of all, when we unveiled our High Bandwidth Compute product portfolio and the multiple generations that we are working on, it is important to understand that it is not something that we just did in one year or so. It was something that has been in the works for the longest period of time. It was last year that I felt like we have reached a point in our R&D where now it is time to commercialize this. Working backwards from there, what is the problem that it is solving? That is something that became quite clear to us by 2021 timeframe.

When we were observing how the compute, in each of these data center racks, and in fact, it also holds true for some of the other places, it is growing quite a bit exponentially, generation over generation, while the memory bandwidth was kind of stagnant or maybe growing more modestly. It is more of a linear growth. It eventually will lead to a memory wall, wherein you can throw as much compute as possible, but it is going to do absolutely nothing when it comes to inference decode portion of it, unless you solve the memory bandwidth as well. We invested quite heavily in our R&D, and when we reached a point where last year where it is becoming like, yeah, now it is feasible. We have cracked a lot of the solutions over there.

Keep in mind that we called it as High Bandwidth Compute because it is not really a pure memory technology. It is actually about a combination of how do you have the compute right next to memory, how do you design it, co-design it in the right way, and then make sure that it interfaces with the rest of the AI accelerator. It was a direct take on an alternative way of doing things as opposed to HBM. We feel very confident and comfortable with where things are right now, and that is why we unveiled our multi-generation solutions, with the first generation coming out next year and the second generation after that.

That is a very unique proposition, and now it is fully endorsed by a large number of the memory vendors as well, who have been our partners for a while, but now they are equally out in the open and talking about something like that.

Okay. Two things over there. First is, some of the numbers and the second part is on proof points, and maybe I will shed a little bit of light in terms of how the discussions are coming up with hyperscalers. In terms of numbers, we always talk about tokens per watt because the power consumption is something that is very important, and today with HBM, the power consumption is very high. By the way, a funny anecdote on that because we talked about 6x improvement compared to HBM in terms of tokens per second per watt. The second part is HBM today is about give or take 21, 22 terabytes per second. We are, like, in hundreds of terabytes per second. When we compared it against SRAM has got its own restrictions. It is the fastest interface, but it consumes more area.

You will need a larger number of racks to do the same thing, so there is a TCO argument to be made against SRAM. These are the three things that we talked about at Investor Day. The important point is, okay, these are numbers. What are the proof points? The nice thing is that, yes, we taped out the silicon. The silicon is back in the lab. It is coming along very well. Stay tuned on that front as we start unveiling this a little bit more on what the numbers are beginning to look like, but we are pretty confident in terms of the first generation of the products. A bit of an anecdote on this. Right after Investor Day, we spoke about this. We said, "Hey, here is HBM." There were these two nice animations, one which talked about, okay, this is no good with HBM.

On the other hand, with HPC, this is great. Right after that, I was in Korea with two memory vendors, and I fully anticipated them to say, "What are you talking about? We have this awesome roadmap with HBM that is really great. It is going to be much better than HPC." That is not the feedback that we received. Instead, what we got is, "Hey, how can we work with you much closer on this?" In fact, we have been working with them because we need to make sure that we have the right supply as we do the commercialization. In addition to that, there has been a lot of interest coming in directly from the memory community itself, which has been a very positive and pleasant experience, and that is actually great.

It also kind of validates some of the points that we made that we need a different kind of a solution as we move forwards in these data center racks. The second generation of the product, so the first generation is slated to be commercial and shipping in 2027. We are already working on the second generation, which is going to be in 2028, and those numbers are even higher. One of the reasons for that, as in terms of the relative comparisons against what we anticipate with HBM4E, the reason for that is as we look ahead to 2028, a lot of things are evolving in itself.

On one hand, AI models themselves are evolving, which means the compute that we end up doing in the compute die or the logic die, which is underneath the DRAM stack, we actually are anticipating what we need to do, and we are throwing in even more arithmetic. It is harder to scale that with HBM, so the relative gain looks even better with that. That is where we are.