Navitas Semiconductor Corporation Common Stock M&A announcement

Gentlemen, take it away. Welcome, and thank you for joining us today to this Breaking the AI Infrastructure Power Wall webcast.

As you surely know, we have closed the Claros acquisition, and this marks a defining step in the Navitas 2.0 transformation. Why does it matter? Power has become a bottleneck for AI compute. Delivering more usable power, more efficiently is an enabler of more compute output. There is a direct link now between power efficiency and compute capacity. In today's webcast, I'm with Llew, our Chief Marketing Officer, as well as Dan, ex-CEO founder of Claros, and now VP GM of the newly created IVR business unit of Navitas. We will cover and explain the power wall, the architectural changes needed to break it, and how Claros completes our technology portfolio. Let me do a brief disclaimer.

Our discussion includes forward-looking statements about our market, technology roadmap, and the expected benefits of the Claros acquisition. This reflects our current expectation and are subject to risk and uncertainty. Please review the disclaimer and the risk described in our SEC filing. Before we get going and go through the presentation, I want to share my excitement in joining forces with Claros and welcome again the entire Claros team to Navitas. As mentioned earlier, this is a very important step in our Navitas 2.0 transformation journey. This is more than just a portfolio addition. Claros connects our existing GaN and SiC capabilities with the critical final stage of power delivery to the processor. Those are complementary technologies. GaN and SiC address conversion and distribution across the higher voltage power chain. Claros brings integrated high-density regulation close to the XPU. We have one single system-level objective.

As the hyperscalers take more and more ownership of the full power chain from grid to XPU, we are now able to serve the entire need with one system-level objective, reduce losses and power density constraint across the chain so that more power can support more AI compute. We think grid-to-XPU really describe well the breadth of our combined portfolio in power and the customer problem we are addressing. Let us start with Navitas 2.0, which we started about a year ago. This is strategic shift away and deliberate pivot from consumer market towards high-power application with AI infrastructure at the center. As a matter of fact, as you might have seen from our past earning release, we expect mobile to be insignificant by the end of 2026, and almost all revenue to come from high power already. Essentially, this means the pivot has happened.

We focus on four markets, AI data center, grid and energy infrastructure, high-performance computing, and industrial electrification. AI infrastructure includes both data center and the energy system supporting, and this is really where the company is heading. We have three technology pillars, GaN for fast, efficient conversion, high voltage and ultra-high voltage SiC for demanding high voltage and high power application, and now Claros IVR for highly integrated power delivery to the processor. Our roots go back to strong technology innovation, as outlined by the number of patents now surpassing 450. This will continue, as well as our strong legacy with over 350 million units shipped. We remain focused on execution and scaling. Our operational priorities continue to be focused on strong and reliable U.S.-based manufacturing and supply chain, supported by our foundry plus model and strategic partnerships that we have announced.

We remain focused on strengthening the financial model through revenue scale, margin expansion and progress towards profitability. As commented at the announcement a few weeks ago, Claros acquisition does not materially change our plan for break-even point. Now that we have integrated Claros, let us review our SAM and long-term opportunity, which is much larger. Our identified 2030 SAM expand from the original $3.5 billion GaN and SiC base to more than $8 billion, including new JFET technology and Claros IVR. We have announced a new JFET product back last summer. What is expanding the market? Approximately $1 billion come from SiC JFET technology, and at least $3.5 billion from the VPD and the IVR opportunity. As you can see, AI infrastructure dominates with more than $6.9 billion and nearly 85% of our SAM, explaining why we outline this as the core focus of the company.

High-performance computing and industrial electrification remains important, but most of these opportunities align directly with our AI infrastructure focus. This is the addressable market, not revenue guidance, but it outlines we are in the right market with the right technology. Our task is now to translate this product portfolio into customer adoption and sustainable growth. Before getting Llew and Dan to go through the details, I want to show you what grid-to-xPU really mean and the overall power AI infrastructure, the architecture coming up. Read the diagram left to right. There are three essential jobs, bring power from the grid to an 800-volt DC infrastructure, convert it efficiently inside the data center, and regulate precisely at the processor at super high current. Grid to 800-volt DC, solid state transformers, battery storage, and power conversion system support efficiency, power density, resilience, and bi-directional energy flow.

Inside the data center, high-density DC-DC conversion steps power down towards the lower voltage rail needed by compute tray, while the 800-volt bus supports distribution. The final step, package and embedded IVR brings power down towards the 0.7 volt processor core, where high current and rapid load change makes delivery essentially demanding. All this together brings one system benefit, higher efficiency, fewer conversion stages, and greater power density. The value comes from improving the whole chain, not just one conversion point. As we discussed earlier, this directly impacts the amount of compute. Now to Llew. Thanks, Chris.

This slide really sets up the problem we are trying to solve. We call it the AI infrastructure power wall. It is a series of compounding challenges from conversion losses and thermal constraints to power density limitations, all the way from the grid to the processor. If we look at today's AI data center power architecture, from left to right, there are challenges developing at every stage. First, we start with traditional line frequency transformers. These have been in existence for over 140 years. They are bulky, heavy, and increasingly incompatible with the power density demanded by modern AI infrastructure. As data center power requirements move into hundreds of megawatts and ultimately gigawatts, the industry needs a much more efficient and scalable way of bringing power from the grid into the data center. Then we move into the AC to DC power supplies.

These convert the AC power to 48 volts DC into the rack. But as the AI rack power continues to increase, these power supplies are reaching practical limits in terms of power density, efficiency, and thermal performance. The next challenge is power distribution. At relatively low voltages, such as 48 volts, delivering more power requires dramatically higher current. As rack power increases, the current flowing through the system quickly becomes enormous, driving significant I squared R losses, heat generation, and the need for impractically large amounts of copper. We see the same issue inside the compute tray. Power still has to be converted from the 48 volts down to 12 volts through an intermediate bus converter or an IBC. This additional DC to DC conversion stage introduces power losses, heat, and additional components that consume valuable board space.

Finally, we reach what is becoming perhaps the most significant power delivery challenge, is the processor itself. Whether that's a GPU, a CPU, a TPU, or even a custom accelerator, these processors are consuming dramatically more power and demanding thousands of amps at sub one volt. When we talk about the AI infrastructure power wall, it isn't a single bottleneck. It's a cumulative effect of limitations across the entire power delivery chain. From the grid to the processor, legacy architectures are becoming pushed beyond what they are designed to support, creating compounding losses, thermal constraints, and power density limitations. As AI power continues to scale, simply improving each stage incrementally is no longer enough. We need to fundamentally rethink the power architecture from the grid all the way to the processor to break through these power walls and enable the next generation of AI compute.